
import chisel3._
import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}

class MyModule(hasE:Boolean, hasS:Boolean, hasW:Boolean, hasN:Boolean) extends Module{

  class MyInterface(
    val hasE:Boolean = true, 
    val hasS:Boolean = true,
    val hasW:Boolean = true,
    val hasN:Boolean = true
  ) extends Bundle{
    val e = if( hasE ) Output(UInt(8.W)) else null
    val s = if( hasS ) Output(UInt(8.W)) else null
    val w = if( hasW ) Output(UInt(8.W)) else null
    val n = if( hasN ) Output(UInt(8.W)) else null
  }

  val io = IO(new MyInterface(hasE, hasS, hasW, hasN))
  val reg = RegInit(10.U(8.W))
  
  if( hasE ) io.e := reg
  if( hasS ) io.s := reg
  if( hasW ) io.w := reg
  if( hasN ) io.n := reg

}

class Top(row:Int, col:Int) extends MyModule {

  val cells = 
    for( i <- 0 until row; j <- 0 until col ){
      val hasE = j!=col-1
      val hasS = i!=row-1
      val hasW = j!=0
      val hasN = i!=0
      yield Module(new MyModule(hasE, hasS, hasW, hasN))
    }

}

object Main extends App{
  override def main(args:Array[String]):Unit = {
    (new chisel3.stage.ChiselStage).execute(
      Array("-X", "verilog"),
      Seq(ChiselGeneratorAnnotation(() => new MyModule(true,false,false,true) )))
  }
}

